Semiconductor memory devices are generally organized in a bi-dimensional array (memory matrix) wherein the memory elements are located at the intersection of rows ("word lines") and columns ("bit lines") of the matrix: to access a given memory element, it is necessary to select the word line and the bit line at the intersection of which said memory element is located; to this purpose, the memory address bus is divided into row and column address signals, which are decoded independently.
In byte- or word-organized memories, having a data bus comprising respectively eight or sixteen bits, each bit in the data bus is associated with a portion of the memory matrix which comprises a group of said bit lines; each logic configuration of the column address signals causes the simultaneous selection of one bit line in each group. Each group of bit lines is associated with a respective sensing circuitry for reading the information stored in the memory matrix elements which belong to said portion of the memory matrix.
It is known that in the manufacture of semiconductor memories, defects are frequently encountered that afflict a limited number of memory elements in the memory matrix. The high probability of defects of this type arises because, in a semiconductor memory device, the greatest part of the chip area is occupied by the memory matrix; moreover, it is in the memory matrix, and not in the peripheral circuitry, that the manufacturing process characteristics are usually pushed to limits.
In order to prevent rejection of an entire chip due to the presence of a limited number of defective memory elements among many millions of memory elements, and therefore to increase the manufacturing process yield, the technique is known of providing for the manufacture of a certain number of additional memory elements, commonly called "redundancy memory elements," to be used as a replacement of those elements that, during testing of the memory device, prove defective. The selection circuits, with which the integrated component must necessarily be provided, and which allow the above-mentioned functional replacement of a defective memory element with a redundancy memory element are indicated as a whole with the name of "redundancy circuitry," while the set of redundancy memory elements and circuitry is defined as "redundancy."
The redundancy circuitry comprises programmable non-volatile memory registers (redundancy registers) suitable to store those address configurations corresponding to the defective memory elements; such registers are programmed once during the memory device testing, and must retain the information stored therein even in absence of the power supply.
In practical implementations of redundancy in memory devices, both word lines and bit lines of redundancy memory elements are generally provided in the memory matrix; each redundancy word line or bit line is associated with a respective redundancy register, wherein the address of a defective word line or bit line is stored so that, whenever the defective word line or bit line is addressed, the corresponding redundancy word line or bit line is selected.
Each redundancy register comprises programmable non-volatile memory cells wherein the address of a defective word- or bit-line can be programmed; each one of such memory cells must comprise at least one programmable non-volatile memory element, such as a fuse or a floating-gate MOSFET, a load circuit for reading the information stored therein, and a program load circuit for the programming of the memory element according to the logic state of a respective address bit in the row or column address signal set. In European Patent Application No. 93830474.8, incorporated herein by reference, provided as background and not admitted as prior art, a program load circuit for the programming of a memory cell in a non-volatile memory register (such as a redundancy register) is described in which the datum to be programmed into the memory element of the memory cell can be directly supplied by one of the address signal lines already present in the memory device for supplying the decoding circuitry, without the need of generating additional signals.
In European Patent Application No. 93830528.1, incorporated herein by reference, provided as background and not admitted as prior art, a redundancy circuitry for a byte- or word-organized memory device is described wherein each redundancy register not only stores the column address of a defective bit line, but also an identifying code for identifying the portion of the memory matrix wherein said defective bit line has been found. As a result, when a defective bit line in a given matrix portion is found, it can be individually replaced by a redundancy bit line, without causing the replacement to occur for all the bit lines in the remaining matrix portions that have the same column address of the defective bit line.
However, when a redundancy register is to be programmed to store the address of a defective bit line, it is necessary to select the redundancy register from among all those available in the redundancy circuitry, and to supply the selected redundancy not only with the column address signals, but also with signals carrying the identifying code of the memory matrix portion to which the defective bit line belongs.